1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
A related-art semiconductor memory device is described taking an EEPROM as an example. FIGS. 8A to 8C are conceptual diagrams of a related-art EEPROM that has a general structure as described in Japanese Patent Application Laid-open No. 2004-71077. FIG. 8A is a plan view, FIG. 8B is a sectional view taken along the line A-A′ of FIG. 8A, and FIG. 8C is a perspective view.
The EEPROM includes a memory main body portion 02 and a select gate transistor portion 01 for selecting the memory main body portion 02. In the memory main body portion 02, an electrode called a floating gate 12, which accumulates electric charges, is formed. The state of the memory is changed depending on an amount of the electric charges. Here, accumulating electric charges in the floating gate 12 puts the memory main body portion 02 into an enhancement mode, which is regarded as a “1” state, and accumulating holes in the floating gate 12 puts the memory main body portion 02 into a depression mode, which is regarded as a “0” state. Writing in the “1” state involves applying a plus voltage called Vpp to a select gate 13 and a control gate 11, setting a drain n+ region 04, a source n+ region 08, and a substrate 05 to GND, and injecting electrons from a tunnel drain n region 06 into the floating gate 12 via a tunnel oxide film 07. Writing in the “0” state involves applying Vpp to the select gate 13 and the drain n+ region 04, setting the control gate 11 and the substrate 05 to GND, setting the source n+ region 08 to a floating voltage, and injecting holes from a tunnel drain n region 06 into the floating gate 12 via the tunnel oxide film 07.
The voltage Vpp in a write needs to be high enough for electric charges to pass through the tunnel oxide film 07. In general, Vpp required when the thickness of the tunnel oxide film is 100 Å is 15 V to 20 V. The voltage Vpp is generated by a booster circuit, which means that all devices from the booster circuit to the memory main body portion 02 need to have a withstand voltage of Vpp or higher. This limitation on withstand voltage is an obstacle to a reduction in device size for the purpose of chip size shrinking, and lowering the voltage Vpp is therefore demanded.
However, if the voltage Vpp is simply lowered, electric charge injection to the floating gate, which is important as a memory function, cannot be accomplished fully. Accordingly, ensuring sufficient injection by thinning the tunnel oxide film 07 is commonly practiced.
The thinning of the tunnel oxide film 07 described above, however, impairs retention characteristics of the memory and accordingly lowers the reliability of the memory.
In addition to this hard-to-overcome trade-off relation, an unnecessary voltage drop in a MOS transistor that is connected in series in a location between the booster circuit and the memory main body portion 02 presents further obstacle to the fulfillment of the request to lower the device withstand voltage. The MOS transistor corresponds to, for example, the select gate transistor portion 01 of FIGS. 8A to 8C.
To give an example, consider a case where, when Vpp is applied to the select gate 13 and the drain n+ region 04 in a write in the “0” state, the electric potential of the tunnel drain n region 06 rises higher than the GND potential of the substrate 05, thereby accidentally applying a back gate voltage to the select gate transistor portion 01, and causing a threshold Vth of the select gate transistor portion 01 to rise to Vth′. Then, the voltage drops by Vth′ in the select gate transistor portion 01 and only a voltage that is lower than Vpp by Vth′ reaches the tunnel train n region 06 (FIG. 10). When, for example, Vth′ is 2 V in the case where a sufficient write requires a voltage application of 15 V to the tunnel drain n region 06, applying Vpp that is 15+2=17 V to the drain n+ region 04 is necessary. In short, Vpp that is higher by 2 V than a voltage of 15V that is normally required for a sufficient write needs to be applied to the drain n+ region 04, which necessitates the securing of excess withstand voltage. In order to eliminate this voltage drop in the select gate transistor portion 01 and set Vpp to 15 V, it is only necessary to apply a voltage higher than Vpp to the select gate 13. However, because this voltage is calculated as Vpp+Vth′=15+2=17 V, securing a withstand voltage of 17 V is still necessary and an excess withstand voltage still needs to be secured, which causes difficulty in reducing device size.
This problem is not limited to the select gate transistor portion 01, and occurs in any MOS transistor that is connected in series between an exit of the booster circuit and the select gate 13. In a write in the “1” state, the same problem occurs in any MOS transistor that is connected in series between the exit of the booster circuit and the control gate 11.
The cause of this problem is the rise in Vth due to the back gate effect, as is understood from the description given above. The degree of rise in Vth due to back gate voltage application is generally determined by a series-capacitance relation between a gate oxide film, which is sandwiched between the gate of the MOS transistor and the substrate, and a semiconductor.
FIG. 9A is a sectional view of the select transistor of FIGS. 8A to 8C (a sectional view taken along the line B-B′). FIG. 9B illustrates an equivalent circuit of FIG. 9A. Denoted by Cox is the gate oxide film capacitance, and denoted by Csi is the semiconductor capacitance that is determined by a thickness d of a depletion layer 14.
When the substrate 05 is dropped to GND and the voltage Vpp is applied to the select gate 13, an electric potential difference of Vpp is generated between the gate and the substrate, the voltage Vpp is divided into Cox and Csi, and Vpp=Vox+Vsi is established. The voltages Vox and Vsi are applied to Cox and Csi, respectively. The degree of rise in Vth is greater when Vox is larger.
The voltage Vox is expressed as (Csi/(Cox+Csi))Vpp. Accordingly, the degree of rise in Vth is greater and the problem described above is graver when Cox is smaller and Cis is larger. In other words, increasing Cox while reducing Csi leads to a solution of the problem. Increasing Cox is accomplished by thinning the gate oxide film 03, but there is a limit to the thinning because of the withstand voltage. Reducing Csi, on the other hand, is accomplished by extending the width d of the depletion layer 14 when a channel is formed, which requires lowering the impurity concentration of the semiconductor substrate. Lowering the impurity concentration also has a limit because of its effect on leakage of the MOS transistor.
Thus, shrinking the chip size by lowering the device withstand voltage is very difficult due to various limitations.